- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371135 > MPC92429FA (MOTOROLA INC) 400 MHz Low Voltage PECL Clock Synthesizer PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC92429FA |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | 400 MHz Low Voltage PECL Clock Synthesizer |
| 中文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 216K |
| 代理商： | MPC92429FA |
MPC92429
TIMING SOLUTIONS
3
MOTOROLA
Table 1. Pin Configuration
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
Analog
Crystal oscillator interface
FOUT, FOUT
Output
LVPECL
Differential clock output
TEST
Output
LVCMOS
Test and device diagnosis output
S_LOAD
Input
0
LVCMOS
Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of
the shift register. The latches will be transparent when this signal is high, thus the
data must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive
S_DATA
Input
0
LVCMOS
Serial configuration data input.
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input.
M[0:8]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
OE
Input
1
LVCMOS
Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the F
OUT
output. OE = L low stops F
OUT
in the logic low state
(F
OUT
= L, FOUT = H)
Negative power supply (GND)
GND
Supply
Supply
Ground
V
CC
Supply
Supply
V
CC
Positive power supply for I/O and core. All V
CC
pins must be connected to the
positive power supply for correct operation
VCC_PLL
Supply
Supply
V
CC
PLL positive power supply (analog power supply)
Table 2. Output frequency range and PLL Post-divider N
N
Output division
di i i
Output frequency range
1
0
0
0
1
200 - 400 MHz
0
1
2
100 - 200 MHz
1
0
4
50 - 100 MHz
1
1
8
25 - 50 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC92429FN | 400 MHz Low Voltage PECL Clock Synthesizer |
| MPC9330 | 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
| MPC962305 | Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305DT-1HR2 | Low-Cost 3.3 V Zero Delay Buffer |
| MPC962309DT-1HR2 | Low-Cost 3.3 V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92429FN | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:400 MHz Low Voltage PECL Clock Synthesizer |
| MPC92432 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:1360 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92432AE | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92432AER2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92432FA | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:1360 MHz Dual Output LVPECL Clock Synthesizer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。