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參數(shù)資料
| 型號： | MPC9229EI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | MPC9229EI |
MPC9229 REVISION 3 AUGUST 6, 2009
5
2009 Integrated Device Technology, Inc.
MPC9229 Data Sheet
400MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
10
—
20
MHz
—
fVCO
VCO Frequency Range(2)
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M ÷ 4.
800
—
1600
MHz
—
fMAX
Output Frequency
N = 00 (
÷ 1)
N = 01 (
÷ 2)
N = 10 (
÷ 4)
N = 11 (
÷ 8)
200
100
50
25
—
400
200
100
50
MHz
—
DC
Output Duty Cycle
45
50
55
%
—
tr, tf
Output Rise/Fall Time
0.05
—
0.3
ns
20% to 80%
fS_CLOCK
Serial Interface Programming Clock Frequency(3)
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. Refer to Applications Information for more details.
0
—
10
MHz
—
tP,MIN
Minimum Pulse Width
(S_LOAD, P_LOAD)
50
—
ns
—
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
—
ns
—
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
—
ns
—
tJIT(CC)
Cycle-to-Cycle Jitter
N = 00 (
÷ 1)
N = 01 (
÷ 2)
N = 10 (
÷ 4)
N = 11 (
÷ 8)
—
90
130
160
190
ps
—
tJIT(PER)
Period Jitter
N = 00 (
÷ 1)
N = 01 (
÷ 2)
N = 10 (
÷ 4)
N = 11 (
÷ 8)
—
70
120
140
170
ps
—
tLOCK
Maximum PLL Lock Time
—
10
ms
—
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