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參數(shù)資料
| 型號： | MPC905EFR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER 1:6 100MHZ 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/無 |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 800-1933-6 |
DATASHEET
1:6 PCI Clock Generator/Fanout Buffer
MPC905
MPC905 REVISION 4 DECEMBER 18, 2012
1
2012 Integrated Device Technology, Inc.
1:6 PCI Clock Generator/
Fanout Buffer
The MPC905 is a six output clock generation device targeted to provide the
clocks required in a 3.3 V or 5.0 V PCI environment. The device operates from a
3.3 V supply and can interface to either a TTL input or an external crystal. The
inputs to the device can be driven with 5.0 V when the VCC is at 3.3 V. The
outputs of the MPC905 meet all of the specifications of the PCI standard.
Features
Six Low Skew Outputs
Synchronous Output Enables for Power Management
Low Voltage Operation
XTAL Oscillator Interface
16-Lead SOIC Package
5.0 V Tolerant Enable Inputs
Replacement part: ICS83905
Functional Description
The MPC905 device is targeted for PCI bus or processor bus environments
with up to 12 clock loads. Each of the six outputs on the MPC905 can drive two
series terminated 50
transmission lines. This capability effectively makes the
MPC905 a 1:12 fanout buffer.
The MPC905 offers two synchronous enable inputs to allow users flexibility in
developing power management features for their designs. Both enable signals are active HIGH inputs. A logic ‘0’ on the
ENABLE1 will pull outputs 0 to 4 into the logic ‘0’ state. A logic ‘1’ on the ENABLE1 input will result in outputs 0 to 4 to be toggling.
A logic ‘0’ on ENABLE2 will cause output BLK5 to a logic ‘0’ state, whereas a logic ‘1’ on ENABLE2 will cause output BLK5 to
toggle. The oscillator remains on.
The ENABLE2 input can be used to disable any high power device for system power savings during periods of inactivity. Both
enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already
LOW. This feature guarantees no runt pulses will be generated during enabling and disabling.
1:6 PCI
CLOCK GENERATOR/
FANOUT BUFFER
SCALE 2:1
D SUFFIX
EF SUFFIX (PB-FREE PACKAGE)
PLASTIC SOIC PACKAGE
CASE 751B-05
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
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