參數(shù)資料
型號: MPC860TCVR66D4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PBGA357
封裝: 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357
文件頁數(shù): 64/81頁
文件大?。?/td> 1618K
代理商: MPC860TCVR66D4
MPC860 PowerQUICC Family Hardware Specifications, Rev. 8
Freescale Semiconductor
67
FEC Electrical Characteristics
13 FEC Electrical Characteristics
This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or
3.3 V.
13.1
MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER,
MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency – 1%.
Table 29 provides information on the MII receive signal timing.
Figure 72 shows MII receive signal timing.
Figure 72. MII Receive Signal Timing Diagram
Table 29. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
5
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK
period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK
period
M1
M2
MII_RX_CLK (Input)
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M3
M4
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