
MPC860 PowerQUICC Family Hardware Specifications, Rev. 8
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Freescale Semiconductor
Bus Signal Timing
Figure 5 provides the timing for the synchronous output signals.
Figure 5. Synchronous Output Signals Timing
Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals.
Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
CLKOUT
Output
Signals
Output
Signals
Output
Signals
B8
B7
B9
B8a
B9
B7a
B8b
B7b
CLKOUT
TS, BB
TA, BI
TEA
B13
B12
B11
B11a
B12a
B13a
B15
B14