參數(shù)資料
型號: MPC860DEVR50D4R2
廠商: Freescale Semiconductor
文件頁數(shù): 27/78頁
文件大小: 0K
描述: IC MPU POWERQUICC 50MHZ 357PBGA
標準包裝: 180
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應商設備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
Freescale Semiconductor
33
Bus Signal Timing
Table 8 provides interrupt timing for the MPC860.
Figure 23 provides the interrupt detection timing for the external level-sensitive lines.
Figure 23. Interrupt Detection Timing for External Level Sensitive Lines
Figure 24 provides the interrupt detection timing for the external edge-sensitive lines.
Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines
Table 8. Interrupt Timing
Num
Characteristic1
1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level-sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the
CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have no direct
relation with the total system interrupt latency that the MPC860 is able to support.
All Frequencies
Unit
Min
Max
I39
IRQx valid to CLKOUT rising edge (setup time)
6.00
ns
I40
IRQx hold time after CLKOUT
2.00
ns
I41
IRQx pulse width low
3.00
ns
I42
IRQx pulse width high
3.00
ns
I43
IRQx edge-to-edge time
4
× TCLOCKOUT
——
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I41
I42
I43
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