參數(shù)資料
型號: MPC859DSLCVR66A
廠商: Freescale Semiconductor
文件頁數(shù): 72/96頁
文件大小: 0K
描述: IC MPU POWERQUICC 66MHZ 357PBGA
標(biāo)準(zhǔn)包裝: 44
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
MPC866/MPC859 Hardware Specifications, Rev. 2
74
Freescale Semiconductor
FEC Electrical Characteristics
Figure 73 shows signal timings during UTOPIA transmit operations.
Figure 73. UTOPIA Transmit Timing
14 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3 V.
14.1 MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum
frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%.
Table 33 shows the timings for MII receive signal.
Figure 74 shows the timings for MII receive signal.
Table 33. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
5
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK period
UtpClk
UTPB
TxEnb
1
2
SOC
5
TxClav
PHSELn
3
4
5
HighZ at MPHY
High-Z at MPHY
U1
U2
U3
U4
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