參數(shù)資料
型號: MPC857DSL
廠商: Motorola, Inc.
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數(shù): 70/88頁
文件大小: 1104K
代理商: MPC857DSL
70
MPC862/857T/857DSL Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
FEC Electrical Characteristics
13.1
MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency - 1%.
Table 29 provides information on the MII receive signal timing.
Figure 73 shows MII receive signal timing.
Figure 73. MII Receive Signal Timing Diagram
13.2
MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency - 1%.
Table 30 provides information on the MII transmit signal timing.
Table 29. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
5
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK period
Table 30. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
5
ns
M6
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
25
M1
M2
MII_RX_CLK (input)
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M3
M4
F
Freescale Semiconductor, Inc.
n
.
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