參數(shù)資料
型號： MPC8572LPXATLD
廠商： Freescale Semiconductor
文件頁數(shù)： 120/138頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.2GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
82
Freescale Semiconductor
PCI Express
16.1
DC Requirements for PCI Express SD1_REF_CLK and
SD1_REF_CLK
For more information, see Section 15.2, “SerDes Reference Clocks.”
16.2
AC Requirements for PCI Express SerDes Reference Clocks
Table 61 lists AC requirements.
16.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
16.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer, Use the PCI Express Base
Specification. REV. 1.0a document.
16.4.1
Differential Transmitter (TX) Output
Table 62 defines the specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 61. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
tREF
REFCLK cycle time
—
10
—
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
—
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge location
–50
—
50
ps
—
Notes:
1. Typical cycle time is based on PCI Express Card Electromechanical Specification Revision 1.0a.
Table 62. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Nominal
Max
Units
Comments
UI
Unit Interval
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not account
for Spread Spectrum Clock dictated variations. See
Note 1.
VTX-DIFFp-p
Differential
Peak-to-Peak
Output Voltage
0.8
—
1.2
V
VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-| See Note 2.
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