參數(shù)資料
型號(hào): MPC8572EVTARNB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 27/138頁
文件大?。?/td> 1502K
代理商: MPC8572EVTARNB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
122
Freescale Semiconductor
Clocking
19.5
Frequency Options
19.5.1
Platform to Sysclk Frequency Options
Table 80 shows the expected frequency values for the platform frequency when using the specified CCB
clock to SYSCLK ratio.
19.5.2
Minimum Platform Frequency Requirements for High-Speed
Interfaces
Section 4.4.3.6 “I/O Port Selection” of the MPC8572E PowerQUICC III Integrated Host Processor
Family Reference Manual, describes various high-speed interface configuration options. Note that the
CCB clock frequency must be considered for proper operation of such interfaces as described below.
For proper PCI Express operation, the CCB clock frequency must be greater than or equal to:
See Section 21.1.3.2, “Link Width” of the MPC8572E PowerQUICC III Integrated Host Processor
Family Reference Manual, for PCI Express interface width details. Note that the “PCI Express link width”
in the above equation refers to the negotiated link width as the result of PCI Express link training, which
may or may not be the same as the link width POR selection.
For proper serial RapidIO operation, the CCB clock frequency must be greater than:
See Section 20.4, “1x/4x LP-Serial Signal Descriptions” of the MPC8572E PowerQUICC III Integrated
Host Processor Family Reference Manual, for serial RapidIO interface width and frequency details.
Table 80. Frequency Options for Platform Frequency
CCB to
SYSCLK Ratio
SYSCLK (MHz)
33.33
41.66
50
66.66
83
100
111
133.33
Platform /CCB Frequency (MHz)
4
400
444
533
5
415
500
555
6
400
498
600
8
400
533
10
417
500
12
400
500
600
527 MHz
PCI Express link width
()
×
8
----------------------------------------------------------------------------------------------
20.80
()
serial RapidIO interface frequency
()
×
serial RapidIO link width
()
×
64
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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