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參數(shù)資料
| 型號： | MPC8572ECVTAVNE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 31/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023FCPBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.5GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤 |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
126
Freescale Semiconductor
System Design Information
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-F ceramic chip capacitor from each SerDes supply (SVDD_SRDSn
and XVDD_SRDSn) to the board ground plane on each side of the device. This should be done for
all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
21.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to VDD,TVDD, BVDD, OVDD, GVDD, and LVDD, as
required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD,TVDD, BVDD,
OVDD, GVDD, and LVDD, and GND pins of the device.
21.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8572E requires weak pull-up resistors (2–10 k
Ω is recommended) on open drain type pins
including I2C pins and MPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 66. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion gives
unpredictable results.
The following pins must NOT be pulled down during power-on reset: DMA_DACK[0:1], EC5_MDC,
HRESET_REQ, TRIG_OUT/READY_P0/QUIESCE, MSRCID[2:4], MDVAL, and ASLEEP. The
TEST_SEL pin must be set to a proper state during POR configuration. For more details, refer to the pinlist
table of the individual device.
21.7
Output Buffer DC Impedance
The MPC8572E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 64). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
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