參數(shù)資料
      型號: MPC8572ECPXATND
      廠商: FREESCALE SEMICONDUCTOR INC
      元件分類: 微控制器/微處理器
      英文描述: 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA1023
      封裝: 33 X 33 MM, PLASTIC, FCBGA-1023
      文件頁數(shù): 111/138頁
      文件大?。?/td> 1502K
      代理商: MPC8572ECPXATND
      MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
      74
      Freescale Semiconductor
      High-Speed Serial Interfaces (HSSI)
      — The external reference clock driver must be able to drive this termination.
      — The SerDes reference clock input can be either differential or single-ended. Refer to the
      Differential Mode and Single-ended Mode description below for further detailed requirements.
      The maximum average current requirement that also determines the common mode voltage range
      — When the SerDes reference clock differential inputs are DC coupled externally with the clock
      driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
      exact common mode input voltage is not critical as long as it is within the range allowed by the
      maximum average current of 8 mA (refer to the following bullet for more detail), since the
      input is AC-coupled on-chip.
      — This current limitation sets the maximum common mode input voltage to be less than 0.4 V
      (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above
      SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
      a clock driver with output driven by its current source from 0 mA to 16 mA (0-0.8 V), such that
      each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
      common mode voltage at 400 mV.
      — If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50
      Ω to
      SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
      must be AC-coupled off-chip.
      The input amplitude requirement
      — This requirement is described in detail in the following sections.
      Figure 44. Receiver of SerDes Reference Clocks
      15.2.2
      DC Level Requirement for SerDes Reference Clocks
      The DC level requirement for the MPC8572E SerDes reference clock inputs is different depending on the
      signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
      below.
      Differential Mode
      — The input amplitude of the differential clock must be between 400mV and 1600mV differential
      peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire
      Input
      Amp
      50
      Ω
      50
      Ω
      SD
      n_REF_CLK
      SD
      n_REF_CLK
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