參數(shù)資料
型號: MPC8572CVTAVND
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 26/138頁
文件大?。?/td> 1502K
代理商: MPC8572CVTAVND
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
121
Clocking
19.4
DDR/DDRCLK PLL Ratio
The dual DDR memory controller complexes can be synchronous with, or asynchronous to, the CCB,
depending on configuration.
Table 79 describes the clock ratio between the DDR memory controller complexes and the DDR PLL
reference clock, DDRCLK, which is not the memory bus clock. The DDR memory controller complexes
clock frequency is equal to the DDR data rate.
When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default
mode of operation is for the DDR data rate for both DDR controllers to be equal to the CCB clock rate in
synchronous mode, or the resulting DDR PLL rate in asynchronous mode.
In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 79 reflects the DDR data rate
to DDRCLK ratio, since the DDR PLL rate in asynchronous mode means the DDR data rate resulting from
DDR PLL output.
Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode.
MPC8572E does not support running one DDR controller in synchronous mode and the other in
asynchronous mode.
010
Reserved
110
3:1
011
3:2 (1.5:1)
111
7:2 (3.5:1)
Table 79. DDR Clock Ratio
Binary Value of
TSEC_1588_CLK_OUT,
TSEC_1588_PULSE_OUT1,
TSEC_1588_PULSE_OUT2 Signals
DDR:DDRCLK Ratio
000
3:1
001
4:1
010
6:1
011
8:1
100
10:1
101
12:1
110
14:1
111
Synchronous mode
Table 78. e500 Core1 to CCB Clock Ratio (continued)
Binary Value of
LWE[0]/LBS[0]/
LFWE, UART_SOUT[1],
READY_P1 Signals
e500 Core1:CCB Clock Ratio
Binary Value of
LWE[0]/LBS[0]/
LFWE, UART_SOUT[1],
READY_P1 Signals
e500 Core1:CCB Clock Ratio
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