參數(shù)資料
型號： MPC8572CVTAULD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
封裝： 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù)： 121/138頁
文件大?。?/td> 1502K
代理商： MPC8572CVTAULD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
83
PCI Express
16.2
AC Requirements for PCI Express SerDes Reference Clocks
Table 58 lists AC requirements.
16.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
16.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer, please use the PCI
EXPRESS Base Specification. REV. 1.0a document.
16.4.1
Differential Transmitter (TX) Output
Table 59 defines the specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 58. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
tREF
REFCLK cycle time
—
10
—
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
—
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge location
–50
—
50
ps
—
Notes:
1. Typical cycle time is based on PCI Express Card Electromechanical Specification Revision 1.0a.
Table 59. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Nominal
Max
Units
Comments
UI
Unit Interval
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not account
for Spread Spectrum Clock dictated variations. See
Note 1.
VTX-DIFFp-p
Differential
Peak-to-Peak
Output Voltage
0.8
—
1.2
V
VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-| See Note 2.
VTX-DE-RATIO
De- Emphasized
Differential
Output Voltage
(Ratio)
–3.0
–3.5
-4.0
dB
Ratio of the VTX-DIFFp-p of the second and following
bits after a transition divided by the VTX-DIFFp-p of
the first bit after a transition. See Note 2.
TTX-EYE
Minimum TX Eye
Width
0.70
—
UI
The maximum Transmitter jitter can be derived as
TTX-MAX-JITTER = 1 - TTX-EYE= 0.3 UI.
See Notes 2 and 3.
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