參數(shù)資料
型號: MPC8572CPXAVNB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, PLASTIC, FCBGA-1023
文件頁數(shù): 49/138頁
文件大?。?/td> 1502K
代理商: MPC8572CPXAVNB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
18
Freescale Semiconductor
Input Clocks
4.4
DDR Clock Timing
Table 7 provides the DDR clock (DDRCLK) AC timing specifications for the MPC8572E.
4.5
Platform to eTSEC FIFO Restrictions
Note the following eTSEC FIFO mode maximum speed restrictions based on platform (CCB) frequency.
For FIFO GMII modes (both 8-bit and 16-bit) and 16-bit Encoded FIFO mode:
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/4.2
EC_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
55
53
%2, 3
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6V and 2.7V
for L/TVDD=3.3V.
2. Timing is guaranteed by design and characterization.
3. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.
EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle
generated by the TSEC
for 10Base-T and 100Base-T reference clock.
Table 7. DDRCLK AC Timing Specifications
At recommended operating conditions with OVDD of 3.3V ± 5%.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
DDRCLK frequency
fDDRCLK
66
100
MHz
1
DDRCLK cycle time
tDDRCLK
10.0
15.15
ns
DDRCLK rise and fall time
tKH, tKL
0.61.0
1.2ns
2
DDRCLK duty cycle
tKHK/tDDRCLK
40
60
%
3
DDRCLK jitter
+/– 150
ps
4, 5, 6
Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex
clock frequency does not exceed the maximum or minimum operating frequencies. Refer to Section 19.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.
6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and
60 kHz on DDRCLK.
Table 6. EC_GTX_CLK125 AC Timing Specifications (continued)
At recommended operating conditions with LVDD/TVDD of 3.3V ± 5% or 2.5V ± 5% (continued)
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
相關PDF資料
PDF描述
MPC8572CVTARND 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA1023
MPC8572ECVTARNB 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA1023
MPC8572ECPXARLD 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA1023
MPC8572ECVTAVLD 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
MPC8572CVTAVND 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
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