參數(shù)資料
型號(hào): MPC8572CPXAUND
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, PLASTIC, FCBGA-1023
文件頁(yè)數(shù): 23/138頁(yè)
文件大?。?/td> 1502K
代理商: MPC8572CPXAUND
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
119
Clocking
The DDR memory controller can run in either synchronous or asynchronous mode. When running in
synchronous mode, the memory bus is clocked relative to the platform clock frequency. When running in
asynchronous mode, the memory bus is clocked with its own dedicated PLL with clock provided on
DDRCLK input pin. Table 75 provides the clocking specifications for the memory bus.
As a general guideline when selecting the DDR data rate or platform (CCB) frequency, the following
procedures can be used:
Start with the processor core frequency selection;
Once the processor core frequency is determined, select the platform (CCB) frequency from the
limited options listed in Table 77 and Table 78;
Check the CCB to SYSCLK ratio to verify a valid ratio can be choose from Table 76;
If the desired DDR data rate can be same as the CCB frequency, use the synchronous DDR mode;
Otherwise, if a higher DDR data rate is desired, use asynchronous mode by selecting a valid DDR
data rate to DDRCLK ratio from Table 79. Please note that in asynchronous mode, the DDR data
rate must be greater than the platform (CCB) frequency. In other words, running DDR data rate
lower than the platform (CCB) frequency in asynchronous mode is not supported by MPC8572E.
Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.
19.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in Table 76:
SYSCLK input signal
Binary value on LA[29:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that, in synchronous mode, the DDR data rate is the determining factor in selecting the CCB bus frequency,
since the CCB frequency must equal the DDR data rate. In asynchronous mode, the memory bus clock
frequency is decoupled from the CCB bus frequency.
Table 75. Memory Bus Clocking Specifications
Characteristic
Min
Max
Unit
Notes
Memory bus clock frequency
200
400
MHz
1, 2, 3, 4
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum
2. The Memory bus clock refers to the MPC8572E memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5] output clocks, running
at half of the DDR data rate.
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. Refer to Section 19.4, “DDR/DDRCLK PLL
Ratio.The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the
DDR data rate.
相關(guān)PDF資料
PDF描述
MPC8572ECPXAUNB 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
MPC8572VTAVLD 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
MPC8572CVTAULD 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
MPC8572EVTATND 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA1023
MPC8572PXAVND 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8572CVTAVNE 功能描述:微處理器 - MPU R211 NoE NoPb 1500 Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572DS 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 MICRO-ATX HIGH PERFORMAN RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類(lèi)型:I2C, SPI, USB 工作電源電壓:
MPC8572EAMC 功能描述:微處理器 - MPU MPC8572 AMC RAPID SYSTEM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572EAMC-SA 制造商:Freescale Semiconductor 功能描述:MPC8572 AMC RAPID SYSTEM - Bulk
MPC8572ECLPXARLE 功能描述:微處理器 - MPU R211 Enc SnPb 1067LP Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324