參數(shù)資料
型號(hào)： MPC8572CLVTAVND
廠商： Freescale Semiconductor
文件頁數(shù)： 24/138頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
12
Freescale Semiconductor
Electrical Characteristics
2.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for this device. Note that the values shown are the
recommended and tested operating conditions. Proper device operation outside these conditions is not
guaranteed.
Table 2. Recommended Operating Conditions
Characteristic
Symbol Recommended Value Unit Notes
Core supply voltage
VDD
1.1 V ± 55 mV
V
—
PLL supply voltage
AVDD
1.1 V ± 55 mV
V
1
Core power supply for SerDes transceivers
SVDD
1.1 V ± 55 mV
V
—
Pad power supply for SerDes transceivers
XVDD
1.1 V ± 55 mV
V
—
DDR SDRAM
Controller I/O
supply voltage
DDR2 SDRAM Interface
GVDD
1.8 V ± 90 mV
V
—
DDR3 SDRAM Interface
1.5 V ± 75 mV
—
Three-speed Ethernet I/O voltage
LVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V4
TVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
4
DUART, system control and power management, I2C, and JTAG I/O voltage
OVDD
3.3 V ± 165 mV
V
3
Local bus and GPIO I/O voltage
BVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Input voltage
DDR2 and DDR3 SDRAM Interface signals
MVIN
GND to GVDD
V2
DDR2 and DDR3 SDRAM Interface reference
MVREFn
GVDD/2 ± 1%
V
—
Three-speed Ethernet signals
LVIN
TVIN
GND to LVDD
GND to TVDD
V4
Local bus and GPIO signals
BVIN
GND to BVDD
V—
Local bus, DUART, SYSCLK, Serial RapidIO, system
control and power management, I2C, and JTAG
signals
OVIN
GND to OVDD
V3
Junction temperature range
TJ
0 to 105
°C—
Notes:
1. This voltage is the input to the filter discussed in Section 21.2.1, “PLL Power Supply Filtering,” and not necessarily the
voltage at the AVDD pin, that may be reduced from VDD by the filter.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
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