- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4036 > MPC8572CLVTAULD (Freescale Semiconductor)MPU POWERQUICC III 1023-PBGA PDF資料下載
參數(shù)資料
| 型號： | MPC8572CLVTAULD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023-PBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.333GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
124
Freescale Semiconductor
System Design Information
21.2
Power Supply Design
21.2.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CORE0, AVDD_CORE1, AVDD_DDR, AVDD_LBIU, AVDD_SRDS1 and
AVDD_SRDS2 respectively). The AVDD level should always be equivalent to VDD, and preferably these
voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 62, one to each of the
AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 1023 FC-PBGA footprint, without the inductance of vias.
Figure 62 shows the PLL power supply filter circuits.
Figure 62. PLL Power Supply Filter Circuit
NOTE
It is recommended to have the minimum number of vias in the AVDD trace
for board layout. For example, zero vias might be possible if the AVDD filter
is placed on the component side. One via might be possible if it is placed on
the opposite of the component side. Additionally, all traces for AVDD and
the filter components should be low impedance, 10 to 15 mils wide and
short. This includes traces going to GND and the supply rails they are
filtering.
The AVDD_SRDSn signal provides power for the analog portions of the SerDesn PLL. To ensure stability
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AVDD_SRDSn ball to ensure it filters out as much noise as possible. The ground connection should be near
the AVDD_SRDSn ball. The 0.003-F capacitor is closest to the ball, followed by the two 2.2 F
capacitors, and finally the 1
Ω resistor to the board supply plane. The capacitors are connected from
VDD
AVDD
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
相關PDF資料 |
PDF描述 |
|---|---|
| MPC8548EVTAVHB | MPU POWERQUICC III 783-PBGA |
| MPC8548EPXAVHB | MPU POWERQUICC III 783-PBGA |
| XC4028XL-2BG352C | IC FPGA C-TEMP 3.3V 2SPD 352MBGA |
| XC4028XL-2BG256I | IC FPGA I-TEMP 3.3V 2SPD 256PBGA |
| FMC40DRYH-S93 | CONN EDGECARD 80POS .100 DIP SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8572CLVTAULE | 功能描述:微處理器 - MPU R211 NoE NoPb 1333LP Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572CLVTAVND | 功能描述:微處理器 - MPU 1500 ExtTmp LwPwr RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572CLVTAVNE | 功能描述:微處理器 - MPU R211 NoE NoPb 1500LP Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572CVTAVNE | 功能描述:微處理器 - MPU R211 NoE NoPb 1500 Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572DS | 功能描述:開發(fā)板和工具包 - 其他處理器 MICRO-ATX HIGH PERFORMAN RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
發(fā)布緊急采購，3分鐘左右您將得到回復。