參數(shù)資料
型號(hào): MPC8569EVTAQLJB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁(yè)數(shù): 11/126頁(yè)
文件大?。?/td> 2847K
代理商: MPC8569EVTAQLJB
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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Enhanced Secure Digital Host Controller (eSDHC)
Freescale Semiconductor
108
2.16.2
eSDHC AC Timing Specifications
The following table provides the eSDHC AC timing specifications as defined in Figure 61 and Figure 62.
Output high voltage
VOH
IOH = –100 μAOVDD –0.2
V
2
Output low voltage
VOL
IOL = 2 mA
0.3
V
2
Input/output leakage current
IIN/IOZ
—–10
10
μA—
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Open drain mode for MMC cards only.
Table 68. eSDHC AC Timing Specifications
At recommended operating conditions with OVDD =3.3 V
Parameter
Symbol1
Min
Max
Unit
Notes
SD_CLK clock frequency:
SD/SDIO full speed/high speed mode
MMC full speed/high speed mode
fSHSCK
0
25/50
20/52
MHz
2, 4
SD_CLK clock low time—High speed/Full speed mode
tSHSCKL
7/10
ns
4
SD_CLK clock high time—High speed/Full speed mode
tSHSCKH
7/10
ns
4
SD_CLK clock rise and fall times
tSHSCKR/
tSHSCKF
3
ns
4, 5
Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK
tSHSIVKH
3.7
ns
3, 4, 6
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
tSHSIXKH
2.5
ns
4, 6
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSHSKHOV
–3
3
ns
4, 6
Notes:
1. The symbols used for timing specifications follow the pattern t(first three letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high
speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the
invalid state (X) or output hold time. Note that in general, the clock reference symbol representation is based on five letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high speed
mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52 MHz for a MMC card.
3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should
not exceed 0.65ns.
4. Ccard
≤10 pF, (1 card) and CL = CBUS + CHOST +CCARD ≤40 pF.
5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
6. The parameter values apply to both full speed and high speed modes.
Table 67. eSDHC Interface DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD =3.3 V
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
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MPC8569EVTAUNLB 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 1.33GHz rev2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MPC8569VJAUNLB 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 1333MHZ 783FCBGA
MPC8569VTANKGB 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 8569 ST 800/600/400 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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