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| 型號： | MPC8568VTANGGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 800 MHz, RISC PROCESSOR, PBGA1023 |
| 封裝： | 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCPBGA-1023 |
| 文件頁數(shù)： | 101/140頁 |
| 文件大?。?/td> | 1456K |
| 代理商： | MPC8568VTANGGA |
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
63
High-Speed Serial Interfaces (HSSI)
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mV p-p.
13.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and
SD_REF_CLK.
The following sections describe the SerDes reference clock requirements and some application
information.
13.2.1
SerDes Reference Clock Receiver Characteristics
Figure 40 shows a receiver reference diagram of the SerDes reference clocks.
SerDes Reference Clock Receiver Reference Circuit Structure
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
in Figure 40. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-
Ω
termination to SCOREGND followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
Differential Mode and Single-ended Mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4V
(0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above SCOREGND.
For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output
driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the
differential input has a single-ended swing from 0V to 800mV with the common mode voltage
at 400mV.
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 ohms to
SCOREGND DC, or it exceeds the maximum input current limitations, then it must be
AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
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