參數(shù)資料
型號: MPC8568ECVTANGGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA1023
封裝: 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 71/139頁
文件大?。?/td> 1449K
代理商: MPC8568ECVTANGGA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
37
Ethernet Interface and MII Management
8.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock
is supplied on TSECn TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,
whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied
on the TSEC_GTX_CLK125 pin in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in Table 33.
A timing diagram for TBI receive appears in Figure 17.
.
Figure 17. TBI Single-Clock Mode Receive AC Timing Diagram
8.2.6
RGMII and RTBI AC Timing Specifications
Table 34 presents the RGMII and RTBI AC timing specifications.
Table 33. TBI single-clock Mode Receive AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
tTRR
7.5
8.0
8.5
ns
RX_CLK duty cycle
tTRRH
40
50
60
%
RX_CLK peak-to-peak jitter
tTRRJ
——
250
ps
Rise time RX_CLK (20%–80%)
tTRRR
—1.0
2.0
ns
Fall time RX_CLK (80%–20%)
tTRRF
—1.0
2.0
ns
RCG[9:0] setup time to RX_CLK rising edge
tTRRDV
2.0
——ns
RCG[9:0] hold time to RX_CLK rising edge
tTRRDX
1.0
——ns
Table 34. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
5
–5006
0
5006
ps
Data to clock input skew (at receiver) 2
tSKRGT
1.0
2.8
ns
Clock period duration 3
tRGT
5
7.2
8.0
8.8
ns
tTRR
tTRRH
tTRRF
tTRRR
RX_CLK
RCG[9:0]
valid data
tTRRDX
tTRRDV
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