參數(shù)資料
型號(hào): MPC8555CVTALF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù): 43/88頁(yè)
文件大小: 772K
代理商: MPC8555CVTALF
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.1
48
Freescale Semiconductor
JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8555E.
Table 38 provides the JTAG AC timing specifications as defined in Figure 32 through Figure 35.
Table 37. CPM I2C Timing (fSCL=400KHz)
Characteristic
Expression
Frequency = 400KHz
Unit
Min
Max
SCL clock frequency (slave)
fSCL
400
KHz
SCL clock frequency (master)
fSCL
-400
KHz
Bus free time between transmissions
tSDHDL
1.2
-
s
Low period of SCL
tSCLCH
1.2
-
s
High period of SCL
tSCHCL
1-
s
Start condition setup time
tSCHDL
420
-
ns
Start condition hold time
tSDLCL
630
-
ns
Data hold time
tSCLDX
420
-
ns
Data setup time
tSDVCH
630
-
ns
SDA/SCL rise time
tSRISE
-250
ns
SDA/SCL fall time
tSFALL
-75
ns
Stop condition setup time
tSCHDH
420
-
ns
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Table 2).
Parameter
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
033.3
MHz
JTAG external clock cycle time
t JTG
30
ns
JTAG external clock pulse width measured at 1.4 V
tJTKHKL
15
ns
JTAG external clock rise and fall times
tJTGR & tJTGF
02
ns
TRST assert time
tTRST
25
ns
3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
0
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
20
25
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
4
20
25
ns
5
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
ns
5
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