參數(shù)資料
型號(hào)： MPC8548VTATHB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 67/142頁
文件大小： 1504K
代理商： MPC8548VTATHB
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
30
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC)
Figure 8 shows the GMII transmit AC timing diagram.
Figure 8. GMII Transmit AC Timing Diagram
8.2.2.2
GMII Receive AC Timing Specifications
Table 27 provides the GMII receive AC timing specifications.
Figure 9 provides the AC test load for eTSEC.
Figure 9. eTSEC AC Test Load
Table 27. GMII Receive AC Timing Specifications
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period
tGRX
—8.0
—
ns
RX_CLK duty cycle
tGRXH/tGRX
35
—
75
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0—
—
ns
RX_CLK clock rise (20%-80%)
tGRXR
2
——
1.0
ns
RX_CLK clock fall time (80%-20%)
tGRXF
2
——
1.0
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive
timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K)
going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
GTX_CLK
TXD[7:0]
tGTKHDX
tGTX
tGTXH
tGTXR
tGTXF
tGTKHDV
TX_EN
TX_ER
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
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