- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25631 > MPC8548HXAVJA (FREESCALE SEMICONDUCTOR INC) 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783 PDF資料下載
參數(shù)資料
| 型號： | MPC8548HXAVJA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, FLIP CHIP, CERAMIC, BGA-783 |
| 文件頁數(shù)： | 127/142頁 |
| 文件大?。?/td> | 1504K |
| 代理商： | MPC8548HXAVJA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁當(dāng)前第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
85
Serial RapidIO
is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std.
802.3ae-2002 is recommended as a reference for additional information on jitter test methods.
17.9.1
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point
at (baud frequency)/1667 is applied to the jitter. The data pattern for template measurements is the
continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-serial
link shall be active in both the transmit and receive directions, and opposite ends of the links shall use
asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane
implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The
amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10–12.
The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V
differential. The left and right edges of the template shall be aligned with the mean zero crossing points of
the measured data eye. The load for this test shall be 100-
Ω resistive ± 5% differential to 2.5 GHz.
17.9.2
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter test
pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-serial link shall be
active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous
clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations
shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured
with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter
tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described
in Annex 48B of IEEE 802.3ae.
17.9.3
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100
Ω resistive ± 5%
differential to 2.5 GHz.
17.9.4
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first
producing the sum of deterministic and random jitter defined in Section 17.7, “Receiver Specifications,”
and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening
of the receive template shown in Figure 54 and Table 65. Note that for this to occur, the test signal must
have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random
jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade
roll-off below this. The required sinusoidal jitter specified in Section 17.7, “Receiver Specifications,” is
then added to the signal and the test load is replaced by the receiver being tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8548VTAVGA | 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783 |
| MPC8548CHXAQG | 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783 |
| MPC8545EVTATGB | 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA783 |
| MPC8543CHXANG | 32-BIT, 800 MHz, MICROPROCESSOR, CBGA783 |
| MPC8543CHXAQG | 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8548HXAVK | 制造商:Freescale Semiconductor 功能描述:PQ38 8548 - Bulk |
| MPC8548PXAQGA | 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT 0.09UM 1GHZ 1.8V/2.5V/3.3V 783-PIN BGA T - Bulk |
| MPC8548PXAQGB | 功能描述:微處理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8548PXAQGD | 功能描述:微處理器 - MPU PQ38 PB ST NE 1000 R3.0 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8548PXATGA | 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT 0.09UM 1.2GHZ 1.8V/2.5V/3.3V 783-PIN BGA - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。