參數(shù)資料
型號： MPC8548HXAVJ
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783
封裝： 29 X 29 MM, 1 MM PITCH, FLIP CHIP, CERAMIC, BGA-783
文件頁數(shù)： 82/142頁
文件大?。?/td> 1504K
代理商： MPC8548HXAVJ
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
44
Freescale Semiconductor
Local Bus
Figure 22 provides the AC test load for the local bus.
Figure 22. Local Bus AC Test Load
NOTE
PLL bypass mode is required when LBIU frequency is at or below 83 MHz.
When LBIU operates above 83 MHz, LBIU PLL is recommended to be
enabled.
Local bus clock to output high Impedance (except LAD/LDP and LALE)
tLBKHOZ1
—2.6
ns
5
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ2
—2.6
ns
5
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4
× BVDD of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
8. Guaranteed by design.
Table 41. Local Bus Timing Parameters (BVDD = 2.5 V)—PLL Enabled (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
BVDD/2
RL = 50 Ω
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8548HXAVK 制造商:Freescale Semiconductor 功能描述:PQ38 8548 - Bulk
MPC8548PXAQGA 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT 0.09UM 1GHZ 1.8V/2.5V/3.3V 783-PIN BGA T - Bulk
MPC8548PXAQGB 功能描述:微處理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8548PXAQGD 功能描述:微處理器 - MPU PQ38 PB ST NE 1000 R3.0 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8548PXATGA 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT 0.09UM 1.2GHZ 1.8V/2.5V/3.3V 783-PIN BGA - Bulk
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