參數(shù)資料
型號: MPC8548EPXAVJA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 53/142頁
文件大小: 1504K
代理商: MPC8548EPXAVJA
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
18
Freescale Semiconductor
RESET Initialization
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8548E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM
component(s).
Table 9 provides the PLL lock times.
5.1
Power-On Ramp Rate
This section describes the AC electrical specifications for the power-on ramp rate requirements. Table 10
provides the power supply ramp rate specifications.
Table 8. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
μs—
Minimum assertion time for SRESET
3
SYSCLKs
1
PLL input setup time with stable SYSCLK before HRESET negation
100
μs—
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
5
SYSCLKs
1
Note:
1. SYSCLK is the primary clock input for the MPC8548E.
Table 9. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Core and platform PLL lock times
100
μs
Local bus PLL lock time
50
μs
PCI/PCI-X bus PLL lock time
50
μs
Table 10. Power Supply Ramp Rate
Parameter
Min
Max
Unit
Notes
Required ramp rate for MVREF
545
Volts/Sec
1
Required ramp rate for VDD/XVDD/SVDD
545
Volts/Sec
1
Note:
1. Ramp rate is specified as a linear ramp. If non-linear (e.g. exponential), ramp rate from near zero to 400 mV is most critical
as this range might falsely trigger the ESD circuitry.
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