參數(shù)資料
型號: MPC8548EPXAQH
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 108/142頁
文件大?。?/td> 1504K
代理商: MPC8548EPXAQH
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
68
Freescale Semiconductor
PCI Express
15.3
SerDes Transmitter and Receiver Reference Circuits
Figure 47 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 47. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
(PCI Express, Serial Rapid IO, or SGMII) in this document based on the application usage:
Note that external an AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in the specification of each protocol section.
16 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E.
16.1
DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
For more information, see Section 15.2, “SerDes Reference Clocks.”
16.2
AC Requirements for PCI Express SerDes Clocks
Table 51 lists the AC requirements for the PCI Express SerDes clocks.
Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typ
Max
Unit
Notes
tREF
REFCLK cycle time
10
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles.
100
ps
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge
location.
–50
50
ps
Note:
1. Typical based on
PCI Express Specification 2.0.
SD_TX
n
SD_TX
n
SD_RX
n
SD_RX
n
50
Ω
Receiver
Transmitter
50
Ω
50
Ω
50
Ω
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