參數(shù)資料
型號(hào): MPC8548EPXAQGB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 56/151頁(yè)
文件大?。?/td> 0K
描述: IC MPU PWRQUICC III 783FCPBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類(lèi)型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.1V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
149
Document Revision History
4
04/2009
moved text, “MII management voltage” from LVDD/TVDD to OVDD, added “Ethernet management” to
OVDD row of input voltage section.
In Table 5, “SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle
time.
In Table 36, “MII Management DC Electrical Characteristics,” changed all instances of LVDD/OVDD to
OVDD.
Modified Section 16, “High-Speed Serial Interfaces (HSSI),” to reflect that there is only one SerDes.
Modified DDR clk rate min from 133 to 166 MHz.
Modified note in Table 75, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.”
In Table 56, “Differential Transmitter (TX) Output Specifications,” modified equations in Comments
column, and changed all instances of “LO” to “L0.” Also added note 8.
In Table 57, “Differential Receiver (RX) Input Specifications,” modified equations in Comments column,
and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “TRX-EYE-MEDIAN-to-MAX-JITTER.”
Added a note on Section 4.1, “System Clock Timing,” to limit the SYSCLK to 100 MHz if the core
frequency is less than 1200 MHz
In Table 71, “MPC8548E Pinout ListingTable 72, “MPC8547E Pinout ListingTable 73, “MPC8545E
Pinout ListingTable 74, “MPC8543E Pinout Listing,” added note 5 to LA[28:31].
3
01/2009
[Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.” Changed
minimum frequency equation to be 527 MHz for PCI x8.
In Table 5, added note 7.
Section 4.5, “Platform to FIFO Restrictions.” Changed platform clock frequency to 4.2.
and add ‘or 2.5 V’ after 3.3 V.
In Table 23, modified table title to include GMII, MII, RMII, and TBI.
In Table 24 and Table 25, changed clock period minimum to 5.3.
In Table 25, added a note.
In Table 26, Table 27, Table 28, Table 29, and Table 30, removed subtitle from table title.
In Table 30 and Figure 15, changed all instances of PMA to TSECn.
In Table 34, Table 35, Figure 18, and Figure 20, changed all instances of REF_CLK to
TSECn_TX_CLK.
In Table 36, changed all instances of OVDD to LVDD/TVDD.
In Table 37, “MII Management AC Timing Specifications,” changed MDC minimum clock pulse width
high from 32 to 48 ns.
Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.” Added new
paragraph.
Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.” Added new
paragraph.
Added information to Figure 63, both in figure and in note.
Table 87, “Part Numbering Nomenclature.” In Silicon Version column added Ver. 2.1.2.
Table 88. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
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