參數(shù)資料
型號(hào): MPC8548ECVUAVJB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
文件頁數(shù): 124/142頁
文件大?。?/td> 1504K
代理商: MPC8548ECVUAVJB
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
82
Freescale Semiconductor
Serial RapidIO
Table 62. Receiver AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential input voltage
VIN
200
1600
mVp-p
Measured at receiver
Deterministic jitter tolerance
JD
0.37
UI p-p
Measured at receiver
Combined deterministic and random
jitter tolerance
JDR
0.55
UI p-p
Measured at receiver
Total jitter tolerance1
JT
0.65
UI p-p
Measured at receiver
Multiple input skew
SMI
24
ns
Skew at the receiver input between lanes
of a multilane link
Bit error rate
BER
10–12
——
Unit interval
UI
800
ps
±100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
Table 63. Receiver AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential input voltage
VIN
200
1600
mVp-p
Measured at receiver
Deterministic jitter tolerance
JD
0.37
UI p-p
Measured at receiver
Combined deterministic and random
jitter tolerance
JDR
0.55
UI p-p
Measured at receiver
Total jitter tolerance1
JT
0.65
UI p-p
Measured at receiver
Multiple input skew
SMI
24
ns
Skew at the receiver input between lanes
of a multilane link
Bit error rate
BER
10–12
Unit interval
UI
400
ps
±100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
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