參數(shù)資料
    型號: MPC8548ECVUAUJB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1333 MHz, MICROPROCESSOR, CBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
    文件頁數(shù): 54/142頁
    文件大?。?/td> 1504K
    代理商: MPC8548ECVUAUJB
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    Freescale Semiconductor
    19
    DDR and DDR2 SDRAM
    6
    DDR and DDR2 SDRAM
    This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
    MPC8548E. Note that GVDD(typ) = 2.5 V for DDR SDRAM, and GVDD(typ) = 1.8 V for DDR2
    SDRAM.
    6.1
    DDR SDRAM DC Electrical Characteristics
    Table 11 provides the recommended operating conditions for the DDR2 SDRAM controller of the
    MPC8548E when GVDD(typ) = 1.8 V.
    Table 12 provides the DDR2 I/O capacitance when GVDD(typ) = 1.8 V.
    Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
    Parameter/Condition
    Symbol
    Min
    Max
    Unit
    Notes
    I/O supply voltage
    GVDD
    1.71
    1.89
    V
    1
    I/O reference voltage
    MVREF
    0.49
    × GVDD
    0.51
    × GVDD
    V2
    I/O termination voltage
    VTT
    MVREF –0.04
    MVREF + 0.04
    V
    3
    Input high voltage
    VIH
    MVREF +0.125
    GVDD +0.3
    V
    Input low voltage
    VIL
    –0.3
    MVREF – 0.125
    V
    Output leakage current
    IOZ
    –50
    50
    μA4
    Output high current (VOUT = 1.420 V)
    IOH
    –13.4
    mA
    Output low current (VOUT = 0.280 V)
    IOL
    13.4
    mA
    Notes:
    1. GVDD is expected to be within 50 mV of the DRAM VDD at all times.
    2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
    noise on MVREF may not exceed ±2% of the DC value.
    3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
    equal to MVREF. This rail should track variations in the DC level of MVREF.
    4. Output leakage is measured with all outputs disabled, 0 V
    VOUT GVDD.
    Table 12. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
    Parameter/Condition
    Symbol
    Min
    Max
    Unit
    Notes
    Input/output capacitance: DQ, DQS, DQS
    CIO
    68
    pF
    1
    Delta input/output capacitance: DQ, DQS, DQS
    CDIO
    —0.5
    pF
    1
    Note:
    1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
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