參數(shù)資料
型號: MPC8547EPXAQJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 45/142頁
文件大?。?/td> 1504K
代理商: MPC8547EPXAQJ
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
139
Document Revision History
23 Document Revision History
Table 84 provides a revision history for the MPC8548E hardware specification.
Table 84. Document Revision History
Revision
Date
Substantive Change(s)
5
10/2009
In Table 27, GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to
35/75 for RX_CLK duty cycle.
Added a reference to Revision 2.1.2.
4
04/2009
moved text, “MII management voltage” from LVDD/TVDD to OVDD, added “Ethernet management” to
OVDD row of input voltage section.
In Table 5, SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle
time.
In Table 36, MII Management DC Electrical Characteristics,” changed all instances of LVDD/OVDD to
OVDD.
Modified Section 15, “High-Speed Serial Interfaces (HSSI),” to reflect that there is only one SerDes.
Modified DDR clk rate min from 133 to 166 MHz.
In Table 52, Differential Transmitter (TX) Output Specifications,” modified equations in Comments
column, and changed all instances of “LO” to “L0.” In addition, added note 8.
In Table 53, “Differential Receiver (RX) Input Specifications,” modified equations in Comments column,
and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “TRX-EYE-MEDIAN-to-MAX-JITTER.”
Added a note on Section 4.1, “System Clock Timing,” to limit the SYSCLK to 100 MHz if the core
frequency is less than 1200 MHz
Pinout ListingTable 70, MPC8543E Pinout Listing,” added note 5 to LA[28:31].
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