參數(shù)資料
型號(hào)： MPC8547ECHXAQJA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
封裝： 29 X 29 MM, 1 MM PITCH, FLIP CHIP, CERAMIC, BGA-783
文件頁數(shù)： 81/142頁
文件大?。?/td> 1504K
代理商： MPC8547ECHXAQJA
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
43
Local Bus
Table 41 describes the timing parameters of the local bus interface at BVDD = 2.5 V.
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ2
—2.5
ns
5
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4
× BVDD of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[
n]. Skew measured between
complementary signals at BVDD/2.
8. Guaranteed by design.
Table 41. Local Bus Timing Parameters (BVDD = 2.5 V)—PLL Enabled
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
12
ns
2
Local bus duty cycle
tLBKH/tLBK
43
57
%
—
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—
150
ps
7, 8
Input setup to local bus clock (except LGTA/UPWAIT)
tLBIVKH1
1.9
—
ns
3, 4
LGTA/LUPWAIT input setup to local bus clock
tLBIVKH2
1.8
—
ns
3, 4
Input hold from local bus clock (except LGTA/LUPWAIT)
tLBIXKH1
1.1
—
ns
3, 4
LGTA/LUPWAIT input hold from local bus clock
tLBIXKH2
1.1
—
ns
3, 4
LALE output transition to LAD/LDP output transition (LATCH hold time)
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—2.1
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—2.3
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—2.4
ns
3
Local bus clock to LALE assertion
tLBKHOV4
—2.4
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
0.8
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
0.8
—
ns
3
Table 40. Local Bus Timing Parameters (BVDD = 3.3 V)—PLL Enabled (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
相關(guān)PDF資料
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MPC8547ECVUAQGB 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
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MPC8547ECPXAQGD 功能描述:微處理器 - MPU PQ38 PB XT WE 1000 R3.0 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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