參數(shù)資料
型號： MPC8545ECVUAQGB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA783
封裝： 29 X 29 MM, 1 MM PITCH, FLIP CHIP, LEAD FREE, CERAMIC, BGA-783
文件頁數(shù)： 37/142頁
文件大?。?/td> 1504K
代理商： MPC8545ECVUAQGB
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
131
System Design Information
21.7
Output Buffer DC Impedance
The MPC8548E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 60). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
Figure 60. Driver Impedance Measurement
Table 82 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,
nominal OVDD, 105°C.
21.8
Configuration Pin Muxing
The MPC8548E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k
Ω on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 k
Ω. This value should permit the 4.7-kΩ resistor to pull
Table 82. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART, Control,
Configuration, Power Management
PCI
DDR DRAM
Symbol
Unit
RN
43 Target
25 Target
20 Target
Z0
W
RP
43 Target
25 Target
20 Target
Z0
W
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
OVDD
OGND
Pad
Data
SW1
SW2
RN
RP
相關(guān)PDF資料
PDF描述
MPC8547CVTATJA 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA783
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