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參數(shù)資料
| 型號： | MPC8545CPXAQGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 34/142頁 |
| 文件大小： | 1504K |
| 代理商： | MPC8545CPXAQGA |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
129
System Design Information
The AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of
the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AVDD_SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near
the AVDD_SRDS ball. The 0.003-F capacitor is closest to the ball, followed by the two 2.2 F capacitors,
and finally the 1
Ω resistor to the board supply plane. The capacitors are connected from AV
DD_SRDS to
the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
should be kept short, wide and direct.
Figure 59. SerDes PLL Power Supply Filter
Note the following:
AVDD_SRDS should be a filtered version of SVDD.
Signals on the SerDes interface are fed from the XVDD power plane.
21.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8548E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin
of the device. These decoupling capacitors should receive their power from separate VDD, TVDD, BVDD,
OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short low impedance traces to
minimize inductance. Capacitors must be placed directly under the device using a standard escape pattern
as much as possible. If some caps are to be placed surrounding the part it should be routed with large trace
to minimize the inductance.
These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD, planes, to enable quick recharging of the
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
for best values, types and quantity of bulk capacitors.
2.2 F 1
0.003 F
1.0
Ω
AVDD_SRDS
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
SVDD
2.2 F 1
GND
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