Table 46 describes " />
參數(shù)資料
型號： MPC8544DVTALF
廠商： Freescale Semiconductor
文件頁數(shù)： 59/117頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCBGA
產(chǎn)品培訓(xùn)模塊： MPC8544E PowerQUICC™ III
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 667MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
配用： MPC8544DS-ND - BOARD DEVELOPMENT SYSTEM 8544
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
46
Freescale Semiconductor
Local Bus
Table 46 describes the general timing parameters of the local bus interface at BVDD = 2.5 V.
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ2
—2.5
ns
5
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4
× BVDD of the signal in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is
programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
Table 46. Local Bus General Timing Parameters (BVDD =2.5 V)—PLL Enabled
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
12
ns
2
Local bus duty cycle
tLBKH/tLBK
43
57
%
—
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—150
ps
7
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
2.4
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
1.8
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.1
—
ns
3, 4
LUPWAIT input hold from local bus clock
tLBIXKH2
1.1
—
ns
3, 4
LALE output transition to LAD/LDP output transition
(LATCH setup and hold time)
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—2.8
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—2.8
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—2.8
ns
3
Local bus clock to LALE assertion
tLBKHOV4
—2.8
ns
3
Output hold from local bus clock (except LAD/LDP and
LALE)
tLBKHOX1
0.8
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
0.8
—
ns
3
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKHOZ1
—2.6
ns
5
Table 45. Local Bus General Timing Parameters (BVDD = 3.3 V)—PLL Enabled (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
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