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參數(shù)資料
| 型號： | MPC8543CPXAQG |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 103/142頁 |
| 文件大?。?/td> | 1504K |
| 代理商： | MPC8543CPXAQG |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
63
High-Speed Serial Interfaces (HSSI)
The input amplitude requirement:
— This requirement is described in detail in the following sections.
Figure 39. Receiver of SerDes Reference Clocks
15.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8548E SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below:
Differential mode
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of
the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.
This requirement is the same for both external DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in Section 15.2.1, “SerDes Reference Clock
Receiver Characteristics,” the maximum average current requirements sets the requirement for
average voltage (common mode voltage) to be between 100 and 400 mV. Figure 40 shows the
SerDes reference clock input requirement for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 41 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from Vmin to Vmax) with
SD_REF_CLK either left unconnected or tied to ground.
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows
the SerDes reference clock input requirement for single-ended signaling mode.
Input
Amp
50
Ω
50
Ω
SD_REF_CLK
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