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    參數(shù)資料
    型號(hào)： MPC8541PXALEX
    廠商： FREESCALE SEMICONDUCTOR INC
    元件分類： 微控制器/微處理器
    英文描述： 32-BIT, 1420 MHz, RISC PROCESSOR, CBGA360
    封裝： 25 X 25 MM, 1.80 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, HCTE, CERAMIC, LGA-360
    文件頁(yè)數(shù)： 60/84頁(yè)
    文件大小： 1241K
    代理商： MPC8541PXALEX
    MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
    Freescale Semiconductor
    63
    Clocking
    15 Clocking
    This section describes the PLL configuration of the MPC8541E. Note that the platform clock is identical
    to the CCB clock.
    15.1
    Clock Ranges
    Table 44 provides the clocking specifications for the processor core and Table 45 provides the clocking
    specifications for the memory bus.
    Table 44. Processor Core Clocking Specifications
    Characteristic
    Maximum Processor Core Frequency
    Unit Notes
    533 MHz
    600 MHz
    667 MHz
    833 MHz
    1000 MHz
    Min
    Max
    Min
    Max
    Min
    Max
    Min
    Max
    Min
    Max
    e500 core
    processor
    frequency
    400
    533
    400
    600
    400
    667
    400
    833
    400
    1000
    MHz 1, 2, 3
    Notes:
    1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
    frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
    frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
    2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
    3. 1000 MHz frequency supports only a 1.3 V core.
    Table 45. Memory Bus Clocking Specifications
    Characteristic
    Maximum Processor Core
    Frequency
    Unit
    Notes
    533, 600, 667, 883, 1000 MHz
    Min
    Max
    Memory bus frequency
    100
    166
    MHz
    1, 2, 3
    Notes:
    1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
    the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
    respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL
    Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
    2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
    3. 1000 MHz frequency supports only a 1.3 V core.
    相關(guān)PDF資料
    PDF描述
    MPC8541ECVTAJDX 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
    MPC8541EPXAQEX 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
    MPC8541CVTAQFX 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360
    MPC8541ECPXAPDX 32-BIT, 1700 MHz, RISC PROCESSOR, CBGA360
    MPC8541EVTALEX 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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    MPC8541PXAPF 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
    MPC8541PXAQF 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
    MPC8541VTAJD 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
    MPC8541VTALF 功能描述:微處理器 - MPU PQ 37 LITE 8555 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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