參數資料
型號: MPC8541ECPXAPDX
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1700 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 2.40 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, HCTE, CERAMIC, BGA-360
文件頁數: 42/84頁
文件大?。?/td> 1241K
代理商: MPC8541ECPXAPDX
MPC8541E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
47
JTAG
Figure 30 provides the AC test load for TDO and the boundary-scan outputs of the MPC8541E.
Figure 30. AC Test Load for the JTAG Interface
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
0
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
20
25
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
4
20
25
ns
5
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
3
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see
Figure 30). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to
the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that,
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design.
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol 2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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