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| 型號： | MPC853TZT100A |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC 100MHZ 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 100MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤 |
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MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor
11
Power Supply and Power Sequencing
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (
ΨJT) can be used. It determines the junction temperature with a measurement of the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
Ψ
JT = thermal characterization parameter
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC using a 40
gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the
package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
8
Power Supply and Power Sequencing
This section provides design considerations for the MPC853T power supply. The MPC853T has a core voltage
(VDDL) and PLL voltage (VDDSYN), which both operate at lower voltages than the I/O voltage VDDH. The I/O
section of the MPC853T is supplied with 3.3 V across VDDH and VSS (GND).
The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO,
TCK, TRST, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than
VDDH. In addition, 5-V tolerant pins can not exceed 5.5 V, and remaining input pins cannot exceed 3.465 V. This
restriction applies to power up/down and normal operation.
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at
different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the
manner in which different voltages are derived. The following restrictions apply:
VDDL must not exceed VDDH during power up and power down.
VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V.
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge
(ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system
power supply design does not control the voltage sequencing, the circuit shown in Figure 2 can be added to meet
these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external
bus and core power supplies on power up and the 1N5820 diodes regulate the maximum potential difference on
power down.
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