
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor
59
CPM Electrical Characteristics
Figure 56. Ethernet Transmit Timing Diagram
Figure 57. CAM Interface Receive Start Timing Diagram
Figure 58. CAM Interface REJECT Timing Diagram
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133
134
132
131
121
129
(NOTE 2)
RCLK3
RxD3
(Input)
RSTRT
(Output)
0
136
125
1
BIT1
BIT2
Start Frame De-
REJECT
137