參數(shù)資料
型號: MPC8536CVTAULA
廠商: Freescale Semiconductor
文件頁數(shù): 70/126頁
文件大小: 0K
描述: MPU PWRQUICC III 1333MHZ 783PBGA
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8536CVTAUL
MPC8536CVTAUL-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
48
This figure shows the MII receive AC timing diagram.
Figure 21. MII Receive AC Timing Diagram
2.9.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
2.9.2.4.1
TBI Transmit AC Timing Specifications
This table provides the TBI transmit AC timing specifications.
This figure shows the TBI transmit AC timing diagram.
Table 32. TBI Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GTX_CLK clock period
tTTX
—8.0
ns
GTX_CLK duty cycle
tTTXH/tTTX
40
60
%
GTX_CLK to TCG[9:0] delay time
tTTKHDX
2
1.0
5.0
ns
GTX_CLK rise (20%–80%)
tTTXR
——
1.0
ns
GTX_CLK fall time (80%–20%)
tTTXF
——
1.0
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high
(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol
representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
2. Data valid tTTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max
Hold)
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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