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| 型號(hào)： | MPC8536BVTAVLA |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 119/126頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MPU PWRQUICC III 1500MHZ 783PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.5GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤(pán) |
| 其它名稱： | MPC8536BVTAVL MPC8536BVTAVL-ND |
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MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
92
peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p
= 2*|VOD|.
6.
Common Mode Voltage, Vcm
The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange
circuit and ground. In this example, for SerDes output, Vcm_out = VSDn_TX + VSDn_TX = (A + B)
/ 2, which is the arithmetic mean of the two complimentary output voltages within a differential
pair. In a system, the common mode voltage may often differ from one component’s output to the
other’s input. Sometimes, it may be even different between the receiver input and driver output
circuits within the same component. It is also referred as the DC offset in some occasion.
Figure 57. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values,
the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each
signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential
swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500
mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage
(VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.20.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks for PCI Express are SD1_REF_CLK and, SD1_REF_CLK. The SerDes reference
clocks for the SATA and SGMII interfaces are SD2_REF_CLK and, SD2_REF_CLK.
The following sections describe the SerDes reference clock requirements and some application information.
2.20.2.1
SerDes Reference Clock Receiver Characteristics
Figure 58 shows a receiver reference diagram of the SerDes reference clocks.
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 58.
Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-
Ω termination to SGND (xcorevss)
followed by on-chip AC-coupling.
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SD
n_TX or
SD
n_RX
SD
n_TX or
SD
n_RX
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Vcm = (A + B) / 2
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