
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
DDR2 and DDR3 SDRAM
Freescale Semiconductor
36
Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 9. Timing Diagram for tDDKHMH
Figure 10 shows the DDR SDRAM output timing diagram.
Figure 10. DDR SDRAM Output Timing Diagram
MDQS
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
tDDKHMH(min) = –0.6 ns
MDQS
ADDR/CMD
tDDKHAS ,tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1
D0
tDDKHAX ,tDDKHCX
Write A0
NOOP
tDDKHME
tDDKHMP