參數(shù)資料
型號： MPC8535CVTATHA
廠商： Freescale Semiconductor
文件頁數(shù)： 123/126頁
文件大小： 0K
描述： MCU PWRQUICC II 1250MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.25GHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8535CVTATH
MPC8535CVTATH-ND
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
96
This figure shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL
driver’s DC levels (both common mode voltages and output swing) are incompatible with chip’s SerDes reference clock input’s
DC requirement, AC-coupling has to be used. This figure assumes that the LVPECL clock driver’s output impedance is 50
Ω.
R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140
Ω to 240Ω depending on
clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
Ω termination resistor to
attenuate the LVPECL output’s differential peak level such that it meets the chip’s SerDes reference clock’s differential input
amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak
is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which
requires R2 = 25
Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with
a particular clock driver chip.
Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC
levels of the clock driver are compatible with chip’s SerDes reference clock input’s DC requirement.
Figure 65. Single-Ended Connection (Reference Only)
50
Ω
50
Ω
SDn_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK
Driver Chip
R2
R1
10nF
10 nF
50
Ω
50
Ω
SDn_REF_CLK
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended
CLK Driver Chip
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8535CVTATLA 功能描述:微處理器 - MPU 8535 NON E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535EAVTAKG 功能描述:微處理器 - MPU 8535E COMMERCIAL 600 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535EAVTAKGA 功能描述:微處理器 - MPU 8535 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535EAVTANG 功能描述:微處理器 - MPU 8535E COMMERCIAL 800 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8535EAVTANGA 功能描述:微處理器 - MPU 8535 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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