參數(shù)資料
型號： MPC8535CVTAKGA
廠商： Freescale Semiconductor
文件頁數(shù)： 43/126頁
文件大小： 0K
描述： MPU POWERQUICC III 783FCPBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 600MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
23
Table 3. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value Unit Notes
Core supply voltage
VDD_CORE
1.0 ± 50 mV
V
—
Platform supply voltage
VDD_PLAT
1.0 ± 50 mV
V
—
PLL core supply voltage
AVDD_CORE
1.0 ± 50 mV
V
2
PLL other supply voltage
AVDD
1.0 ± 50 mV
V
2
Core power supply for SerDes transceivers
SVDD
1.0 ± 50 mV
V
—
Pad power supply for SerDes transceivers and PCI Express
XVDD
1.0 ± 50 mV
V
—
DDR SDRAM
Controller I/O supply
voltage
DDR2 SDRAM Interface
GVDD
1.8 V ± 90 mV
V
3
DDR3 SDRAM Interface
1.5 V ± 75 mV
Three-speed Ethernet I/O voltage
LVDD
(eTSEC1)
3.3 V ± 165 mV
2.5 V ± 125 mV
V5
TVDD
(eTSEC3)
3.3 V ± 165 mV
2.5 V ± 125 mV
PCI, DUART, system control and power management, I2C, USB, eSDHC,
eSPI and JTAG I/O voltage, MII management voltage
OVDD
3.3 V ± 165 mV
V
4
Local bus I/O voltage
BVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Input voltage
DDR2 and DDR3 SDRAM Interface signals
MVIN
GND to GVDD
V3
DDR2 and DDR3 SDRAM Interface reference
MVREF
GVDD/2 ± 1%
V
—
Three-speed Ethernet signals
LVIN
TVIN
GND to LVDD
GND to TVDD
V5
Local bus signals
BVIN
GND to BVDD
V—
PCI, Local bus, DUART, SYSCLK, system control
and power management, I2C, and JTAG signals
OVIN
GND to OVDD
V4
Operating
Temperature range
Commercial
TA
TJ
TA= 0 (min) to
TJ= 90(max)
°C6
Industrial
standard temperature range
Extended temperature range
TA= 0 (min) to
TJ= 105 (max)
TA= -40 (min) to
TJ= 105 (max)
Notes:
2. This voltage is the input to the filter discussed in Section 3.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage
at the AVDD pin, which may be reduced from VDD by the filter.
3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
6. Minimum temperature is specified with T
A; maximum temperature is specified with TJ.
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