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參數(shù)資料
型號: MPC8535AVTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 53/126頁
文件大小: 0K
描述: MPU POWERQUICC III 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
32
This table provides the DDR capacitance when GVDD(type) = 1.8 V.
This table provides the current draw characteristics for MVREF.
2.6.2
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The DDR controller supports
both DDR2 and DDR3 memories. Please note that although the minimum data rate for most off-the-shelf DDR3 DIMMs
available is 800 MHz, JEDEC specification does allow the DDR3 to run at the data rate as low as 606 MHz. Unless otherwise
specified, the AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and
667 MHz, as long as the DC and AC specifications of the DDR3 memory to be used are compliant to both JEDEC specifications
as well as the specifications and requirements described in this document.
2.6.2.1
DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
These tables provide the input AC timing specifications for the DDR controller.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
1, 2
Delta input/output capacitance: DQ, DQS, DQS
CDIO
0.5
pF
1, 2
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V (for DDR2), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT
(peak-to-peak) = 0.2 V.
2. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT
(peak-to-peak) = 0.175 V.
Table 15. Current Draw Characteristics for MVREF
Parameter/Condition
Symbol
Min
Max
Unit
Note
Current draw for MVREFn
DDR2 SDRAM
IMVREFn
1500
μA1
DDR3 SDRAM
1250
1.The voltage regulator for MVREF must be able to supply up to 1500 μA or 1250 uA current for DDR2 or DDR3 respectively.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 V ± 5%
Parameter
Symbol
Min
Max
Unit
AC input low voltage
667
VILAC
—MVREF – 0.20
V
<=533
MVREF – 0.25
V
AC input high voltage
667
VIHAC
MVREF + 0.20
V
<=533
MVREF + 0.25
V
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