參數(shù)資料
型號： MPC8535AVTAKG
廠商： Freescale Semiconductor
文件頁數(shù)： 52/126頁
文件大小： 0K
描述： MCU PWRQUICC II 600MHZ 783-PBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 600MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
31
2.6
DDR2 and DDR3 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip. Note that DDR2
SDRAM is GVDD(type) = 1.8 V and DDR3 SDRAM is GVDD(type) = 1.5 V.
2.6.1
DDR2 and DDR3 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR SDRAM component(s) of the chip when interfacing to
DDR2 SDRAM.
This table provides the recommended operating conditions for the DDR SDRAM controller of the chip when interfacing to
DDR3 SDRAM.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.7
1.9
V
1
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
V2
I/O termination voltage
VTT
MVREF –0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF+0.125
GVDD +0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.125
V
—
Output leakage current
IOZ
–50
50
μA4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the chip. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ VOUT ≤ GVDD.
Table 13. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.425
1.575
V
1
I/O reference voltage
MVREFn
0.49
× GVDD
0.51
× GVDD
V2
Input high voltage
VIH
MVREFn + 0.100
GVDD
V—
Input low voltage
VIL
GND
MVREFn – 0.100
V
—
Output leakage current
IOZ
–50
50
μA3
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREFn is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREFn may not exceed ±1% of the DC value.
3. Output leakage is measured with all outputs disabled, 0 V
≤ VOUT ≤ GVDD.
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