參數(shù)資料
型號: MPC852TCZT100A
廠商: Freescale Semiconductor
文件頁數(shù): 28/80頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 100MHZ 256PBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 100MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC852T PowerQUICC Hardware Specifications, Rev. 4
34
Freescale Semiconductor
Bus Signal Timing
Table 10 provides interrupt timing for the MPC852T.
.
Figure 24 provides the interrupt detection timing for the external level-sensitive lines.
Figure 24. Interrupt Detection Timing for External Level Sensitive Lines
Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.
Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines
Table 10. Interrupt Timing
Num
Characteristic1
1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level-sensitive. The IRQ lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and have no direct
relation with the total system interrupt latency that the MPC852T is able to support.
All Frequencies
Unit
Min
Max
I39
IRQx valid to CLKOUT rising edge (set up time)
6.00
ns
I40
IRQx hold time after CLKOUT
2.00
ns
I41
IRQx pulse width low
3.00
ns
I42
IRQx pulse width high
3.00
ns
I43
IRQx edge-to-edge time
4
× TCLOCKOUT
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I41
I42
I43
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