參數(shù)資料
型號： MPC850CZQ50BUR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC PROCESSOR, PBGA256
封裝： 23 X 23 MM, 1.27 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 9/75頁
文件大?。?/td> 2995K
代理商： MPC850CZQ50BUR2
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
17
Bus Signal Timing
B33a
CLKOUT rising edge to GPL
valid - as requested by control
bit GxT3 in the corresponding
word in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B34
A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST4 in the corresponding
word in the UPM
3.00
—
6.00
—
4.00
—
0.250
50.00
ns
B34a
A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST1 in the corresponding
word in the UPM
8.00
—
13.00
—
11.00
—
0.500
50.00
ns
B34b
A[6–31] and D[0–31] to CS valid
- as requested by CST2 in the
corresponding word in UPM
13.00
—
21.00
—
17.00
—
0.750
50.00
ns
B35
A[6–31] to CS valid - as
requested by control bit BST4 in
the corresponding word in UPM
3.00
—
6.00
—
4.00
—
0.250
50.00
ns
B35a
A[6–31] and D[0–31] to BS valid
- as requested by BST1 in the
corresponding word in the UPM
8.00
—
13.00
—
11.00
—
0.500
50.00
ns
B35b
A[6–31] and D[0–31] to BS valid
- as requested by control bit
BST2 in the corresponding
word in the UPM
13.00
—
21.00
—
17.00
—
0.750
50.00
ns
B36
A[6–31] and D[0–31] to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
3.00
—
6.00
—
4.00
—
0.250
50.00
ns
B37
UPWAIT valid to CLKOUT
falling edge 10
6.00
—
6.00
—
6.00
—
50.00
ns
B38
CLKOUT falling edge to
UPWAIT valid 10
1.00
—
1.00
—
1.00
—
50.00
ns
B39
AS valid to CLKOUT rising edge
11
7.00
—
7.00
—
7.00
—
50.00
ns
B40
A[6–31], TSIZ[0–1], RD/WR,
BURST, valid to CLKOUT rising
edge.
7.00
—
7.00
—
7.00
—
50.00
ns
B41
TS valid to CLKOUT rising edge
(setup time)
7.00
—
7.00
—
7.00
—
50.00
ns
Table 6. Bus Operation Timing 1 (continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
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