參數(shù)資料
型號： MPC8379EVRALGA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù)： 74/114頁
文件大小： 1337K
代理商： MPC8379EVRALGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
62
Freescale Semiconductor
Serial ATA (SATA)
Table 56 provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA
interface.
15.3.2
Gen2i/3G Receiver (Rx) Specifications
Table 57 provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 58 provides the differential receiver output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Table 56. Gen 1i/1.5G Receiver AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Unit interval
TUI
666.4333
666.667
670.2333
ps
—
Total jitter, data-data
5UI
USATA_TXTJ5UI
—
0.43
UIp-p
1
Total jitter, data-data
250 UI
USATA_TXTJ250UI
—
0.60
UIp-p
1
Deterministic jitter, data-data
5UI
USATA_TXDJ5UI
—
0.25
UIp-p
1
Deterministic jitter, data-data
250 UI
USATA_TXDJ250UI
—
0.35
UIp-p
1
Note:
1 Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 57. Gen2i/3G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
VSATA_RXDIFF
275
500
750
mVp-p
1
Differential RX input impedance
ZSATA_RXSEIM
85
100
115
Ω
—
Note:
1 Voltage relative to common of either signal comprising a differential pair.
Table 58. Gen 2i/3G Receiver AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Channel Speed
tCH_SPEED
—3.0
—
Gbps
—
Unit Interval
TUI
333.2
333.33
335.11
ps
—
Total jitter
fC3dB =fBAUD/10
USATA_TXTJfB/10
—
0.46
UIp-p
1
Total jitter
fC3dB =fBAUD/500
USATA_TXTJfB/500
—
0.60
UIp-p
1
Total jitter
fC3dB =fBAUD/1667
USATA_TXTJfB/1667
—
0.65
UIp-p
1
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